Phase inverter circuit



SePt- 10, 1957 F. J. lANNoNE 2,806,151

PHASE INVERTERCIRCUIT Filed Dec. 14, 1954 ,faire /A/'l/AZOL- @5MM M Jmafaf() QM United States Patent O PHASE INVERTER CIRCUIT Francis J. Iannone, Culver City, Calif., assigner to The National Cash Register Company, Dayton, (litio, :i corporation of Maryland Appiication December' 14, 1954, Serial No. 475,182

Claims. (Cl. 307-88) This invention relates to phase inverter circuits and more particularly to an electrical circuit arrangement in which reactive components are employed to function as a phase inverter circuit. i

Circuits utilizing reactive components therein, e. g., saturable core reactors, possess a high degree of reliability and utility inasmuch as they contain no fragile parts, and their maintenance is comparable to that of a conventional transformer. Furthermore, the power requirement of such devices is relatively low and they can be operated in an enclosed area without the need of supplementary cooling means. Since phase inverter circuits have numerous applications in the electronic computer art, as, for example, in the formation of digital complements, it is highly desirable to provide a reactive type phase inverter circuit.

One of the objects of this invention is to provide a highly sensitive phase inverter circuit whose output has a sharp response to abrupt changes in voltage signals applied on the input.

It is another object of this invention to provide a saturable core type phase inverter circuit which serves to amplify the inverted signal generated on the output thereof.

It is still another object of this invention to provide a novel electrical circuit arrangement comprised of reactive components which can be adapted to function as a comparison circuit.

Briefly, the invention herein disclosed comprises a nonlinear resonance path including a saturable core inductor connected in series with a capacitor. A source of alternating potential is connected to this path. The junction between the saturable core inductor and the capacitor is connected to a highly sensitive loading means, e. g., the winding of another saturable core inductor which includes a capacitor in parallel therewith so as to effectively form a tank circuit. A second capacitor is connected in series with this tank circuit. A control winding is included about the s'aturable reactor in the tank circuit. The operation of the inverter circuit is such that the series non-linear resonance path is normally maintained in a relatively high current conducting state when the control winding has a relatively low D. C. voltage signal applied thereon. The effect of applying a lrelatively high D. C. voltage signal to the control winding of the saturable reactor in the tank circuit is to instantaneously load the series non-linear resonance path such that its operation switches to a relatively low current conducting state. An A. C. output signal is taken from the junction between the inductor and capacitor of the series nonlinear resonance path. This A. C. output signal is rectiiied and filtered so as to provide a D. C. output signal which is the inverse of the D. C. input signal.

A more detailed description of this invention as well as additional objects and features thereof is contained in the following explanation of the drawings in which:

Fig. 1 is a schematic diagram of the invention.

Fig. 2 is an idealized graph for explaining the theory of operation of the circuit shown in Fig. l.

Fig. 3 is a schematic diagram of a circuit arrangement showing how the embodiment of Fig. 1 can be adapted to function as a digital comparison circuit.

Reference will first be made to Fig. 1, which shows a schematic diagram of a preferred embodiment of the invention. This phase inverter circuit comprises a series non-linear resonance path P, including a non-linear saturable core inductor L1 connected in series with a capacitor C1. A source of alternating potential is applied to path P at terminal 1. This source of alternating potential and the value of the components in path P are chosen so as to normally maintain path P in a highly conductive state in accordance with the principles of ferroresonance.

Connected to junction 6 which is located between nonlinear inductor L1 and capacitor C1 of path P is a highly sensitive loading means. In this embodiment of the invention, the loading means comprises a tank circuit, i. e., non-linear inductor L2 in parallel with capacitor C2; a capacitor C3 connects the tank circuit to ground. It is to be noted that non-linear inductors L1 and L2 are preferably of a solenoidal type, having a rolled scroll type Permalloy core with a lengthtodiameter ratio on the order of ten to one. A control winding 4 is wound about core 5 of inductor L2. The D. C. input signal which is to be inverted is applied on terminal 9 of control winding 4, while the opposite end of control winding 4 is grounded.

Alternating current output from the phase inverter is taken from junction 6 by way of lead 2. This alternating current output is then rectified by means of diode 3. The cathode equivalent end of diode 3 is connected to a lter circuit made up of the parallel combination of resistor R1 and capacitor C4. The filtered D. C. output signal corresponding to the inverse of the input signal is thus available on lead 8 which is an extension of lead 2. Diodes D1 and D2, shown dotted in the figure, connect lead 8 to D. C. voltage levels e1 and e2, respectively. The provision of diodes D1 and D2 is optional, their use being dependent upon whether it is desired to limit the swing of the output signal.

The current through control winding 4 is termed control current and will be herein identified by the symbol Ic; similarly the voltage appearing on output lead 8 is termed output voltage and is designated E0.

The operation of the invention shown in Fig. l can be more readily explained by reference to Fig. 2 which is an idealized plot of control current Ic versus output Voltage ss n o. As indicated by point a, the parameters of nonlinear resonance path P are such that its output voltage E0 is normally in a relatively high state in the absence of any substantial control current Ic applied to input terminal 9. Point a thus occurs on the high E@ voltage hump of the curve of Fig. 2 because in the absence of any substantial control current Ic applied to input terminal 9, parameters of the parallel circuit combination of saturable core inductor L2 and capacitor C2 are such as to cause the tank circuit to tend toward parallel resonance at the frequency of the applied A. C., i. e., to present a relatively high impedance to current between path P and ground. Consequently only negligible current passes from junction 6 to ground by way of series capacitor C3.

However, when an input signal of amplitude suficient to effect a value of control current Ic greater than a certain threshold value, herein designated It, is applied to input terminal 9, the output voltage E0 sharply drops to a relatively low value prepresented by point b, for example, in thegraph of Fig. 2. This abrupt fall in output voltage E,o occurs owing to the elect of increased control current Ic through control winding 4 on saturable core 5, i. e., current Ic nearly saturates core 5 with magnetic ux lines. The inductance of non-linear inductor L2 is consequently reduced, effecting relatively high current through capacitor Ca. The value of capacitor Ca is so chosen that the Lz-Ca series combination nowtends toward series resonance. The voltage appearing at junction 6 is lowered thereby and non-linear resonance path P is electively loaded into its relatively low conducting state, i. e., operating at point b on the graph of Fig. 2.

Output voltage En therefore sharply drops to a lower level b and continues at that level until control current Ie is substantiallyrreduced, thereby causing current cessation through capacitor Cs.Y Path P is now effectively returned to a relatively high conducting state a owing to the relatively high Vvoltage now appearing at junction 6. Thus an amplified waveform signal can be effected on output lead 8 which is the inverse of the waveform applied at input terminal 9, for example.

As a typical example of the operation of the phase inverter circuit shown in Fig. 1, assume a binary inputv waveform signal 0101, herein designated S1, is applied to control winding 4 at input terminal 9. Assume that a low voltage level e, is representative of a binary zero while a high voltage level e2 is representative of a binary one Time scale is assumed to be from left to right; furthermore, high voltage level e2 is of value suficient to effect a control current Ic in control winding 4 that is greater in value than threshold current It, e. g., e. .=-l25 volts; similarly, the low voltage level e1 is of value insuicient to elect appreciable control current Ic, e. g., e,=0 volts.

During the 0 volt level of input signal S1, the A. C. voltage appearing on lead 2 is relatively high, as the first one in A. C. waveform S2 indicates. But when the input waveform signal S1 rises to its one level, i. e., from e, to e2, sufficient control current Ic is passed through control winding 4 to load non-linear resonance path P to its relatively low or zero state, i. e., point "b on graph of Fig. 2. Appreciable current now passes through capacitor C3 because the Lz-Ca combination tends toward series resonance. When input signal S1 returns to a 0 voltage level, however, i. e., back to e1, the combination of Lz-Cz tends toward non-linear parallel resonance, eiecting a voltage rise at junction 6 since capacitor C3 now presents a high impedance. The A. C. signal S2 consequently attains its high voltage or one state again and continues at this high level until path P is again loaded into a low or zero state by a subsequent rise of input signal S1 to voltage level e2. Thus a D. C. input Isignal S1 of configuration 0101, for example, applied to control winding 4 elects an amplified A. C. signal S2 on lead 2 of inverse configuration, i. e., 1010.

This amplilied A. C. signal Sz is then rectified by means of diode 3 and smoothed by a iilter circuit such as that comprised of the parallel combination of resistor R1 and capacitor C4, for example. The result is D. C. signal S3, appearing on output lead 8. Output signal S3 is thus the inverse or complement of input signal S1, e. g., 1010 is the ones complement of 0101.

It is to be noted that the output waveform Sa, appearing on lead 8, can be clamped as indicated by diodes D1 and Dz which are shown dotted in Fig. 1 inasmuch as they are not essential components of the invention. Use of these output clampers enables the voltage swing of the output waveform signal Sa to be maintained within the limits of the input signal S1. This result is achieved by utilization of corresponding clamping voltages e, and e2 applied to the cathode of diode D1 and the anode of diode D2, respectively. Thus means is provided for converting a typical binary signal sequence such as 0101, for example, into its complement 1010 for subsequent use in logical networks, e. g., ,diode gating operations dependent upon a plurality of input signals, each swinging between two voltage levels such as e1 and e2, for example.

In the schematic diagram comprising Fig. 3, an alternate embodiment of the invention is shown with its control winding adapted to operate as a novel gating circuit such that the overall circuit arrangement functions as a comparison circuit. Inasmuch as the operation of this circuit is substantially the same as was previously explained in conjunction with Fig. 1, like elements thereof bear similar reference designations, but with a prime added thereto.

Two input leads 10 and 11 are provided to the control winding which is divided by means of grounded centertap 14 into subwindings 12 and 13, each having the same number of turns therein. A current unbalance in subwindings 12 and 13 is necessary in order to obtain an output signal from the trigger winding. Thus when two substantially identical signal inputs are simultaneously applied to input leads 10 and 11, no effective control current output is obtained, owing to the substantially equalvalued bucking voltages set up in subwindings 12 and 13, respectively, of this control winding.

In summary, the gating operation of the control winding arrangement set forth in Fig. 3 is such that elective control current lc will be induced in saturable reactor L2' only when different polarity signals are simultaneously applied to input leads 10 and 11. This effect is illustrated by the serial waveform signals 0101 and 0110 applied simultaneously to inputs 10 and 11, respectively, yielding the amplified output signal 1100, as shown. Of course, this is but one representative example of the operation of this circuit which is commonly termed a comparison circuit. Furthermore, the output voltage appearing on lead 8 can be clamped if so desired, as was explained in conjunction with Fig. l.

A comparison circuit of the type presented in Fig. 3 is especially useful in error indication, for example, between two identical circuits which are simultaneously computing the same problem.

ln the foregoing specification, a low power, saturable core phase inverter circuit has been presented. Of course, the specific apparatus and circuits just described represent but one form of this invention and are not to be interpreted as a restriction or limitation thereof. It is apparent that modifications and variations of this phase inverter circuit may occur to those skilled in the electronic art without departing from the spirit and scope of this invention as defined in the appended claims.

What is claimed is:

1. A phase inverter circuit comprising a ferro-resonant path including a -saturable reactor and a series lcapacitance; a source of A. C. potential applied to said path such that said path is normally in a high-current conducting state; an output circuit connected across the capacitance of said ferro-resonant path so as to normally have high level potential signals thereon; a source of high level potential input signals; and means connected across the capacitance or said path capable of responding to said high level potential input signals for maintaining said ferro-resonant path in a low-current conducting state so as to generate low level potential signals on said output circuit.

2. A phase inverter circuit comprising the combination of a series resonant circuit arrangement of a capacitance and a saturable core inductor; a parallel resonant circuit arrangement of a secondcapacitance and a second saturable core inductor; means including a third capacitance connecting said parallel circuit arrangement across the capacitance of said series circuit arrangement; control means inductively coupled to said second saturable core inductor for changing the degree of saturation thereof between one ydegree at which said parallel circuit arrangement is resonant and another degree at which said parallel circuit arrangement is non-resonant; and an output circuit connected across the capacitance of said series circuit arrangement.

3. A phase inverter circuit comprising a rst ferroresonant circuit including a capacitance connected in series with a non-linear inductor; a source of alternating potential connected to said first 'ferro-resonant circuit; a second ferro-resonant circuit including a capacitance connected in parallel with a non-linear inductor; a third capacitance connected in series with said second ferro-resonant circuit across the capacitance of said first ferro-resonant circuit; control means coupled to said second nonlinear inductor to change the effective inductance thereof; and an output connected across the capacitance of said first ferro-resonant circuit, said circuits having capacitances and inductors of such value and being so operated that a control signal applied to said control means produces an amplified phase inverted signal on said output.

4. A 4comparison circuit comprising a first non-linear resonant branch includingr a saturable core inductor connected in series with a capacitance; a second non-linear resonant branch including a second -saturable core inductor connected in parallel with a second capacitance; a third capacitance connected in series with said second non-linear resonant branch; a control Winding about the core of said second saturable core inductor, said control winding having a centertap connected to ground reference potential; a control input connected to each end of said control winding; means for connecting the series circuit formed by said second non-linear resonant branch and said third capacitance across the capacitance of said first nonlinear resonant branch; and an output circuit including a rectier and iilter circuit connected across the capacitance of said first non-linear resonant branch, whereby an output signal is generated on said output circuit when an input signal is applied on only one of said control inputs.

5. Apparatus of the class described comprising: a ferroresonant path including a non-linear inductor and a capacitance in series therewith; an alternating potential applied across said ferroresonant path such that said path is normally in a relatively high-current conducting state; an impedance control circuit connected across the capacitance of said ferroresonant path, said control circuit including a second non-linear inductor connected in parallel with a second capacitance and in series with a third capacitance, said control circuit normally operating with a high impedance; input means coupled to said second non-linear inductor; and a source of signals connected to said input means to decrease the inductance of said second non-linear inductor, thereby decreasing the irnpedance of said control circuit to cause said ferroresonant path to operate in a relatively low-current conducting state for the duration of each signal applied to said input means.

6. A circuit of the class described comprising: an alternating voltage source; a series non-linear circuit including a saturable core inductor and a capacitance connected to said alternating voltage source, said series circuit normally operating in a resonant conduction state; an output circuit connected across the capacitance of said series circuit; a control circuit including .a second saturable core inductor connected across said output circuit: and means for changing the impedance of said control circuit by saturating the core of said second saturable core inductor to thereby load said series circuit into a nonresonant conduction state.

7. A phase inverted signal generator comprising: an

.6 alternating voltage source; a series resonant non-linear circuit including a saturable core inductor and a capacitance connected to said alternating voltage source; a control circuit for said series circuit including a second saturable core inductor connected across the capacitance thereof, said control circuit normally having a high impedance; a source of control signals; a control winding for saturating the core of said second saturable core inductor in response to said control signals to reduce the impedance of said control circuit; and an output circuit connected across the capacitance of said series circuit having phase inverted signals produced thereon in response to control signals on said control winding.

8. A phase inverter amplifier comprising: an alternating voltage source; a series non-linear circuit including a saturable core inductor and a capacitance connected to said alternating voltage source, said series circuit normally energized to operate in series resonance; a parallel nonlinear circuit including a second saturable core inductor connected in parallel with a second capacitance; means for connecting said parallel circuit in series across the capacitance of said series circuit, said parallel circuit being normally energized to operate in parallel resonance; a control winding about the core of said second saturable core inductor; and a source of control signals connected to said control Winding, whereby said parallel circuit becomes non-resonant in response to a control signal, thereby causing said series circuit to be loaded into a nonresonant condition.

9. A phase inverted signal generator comprising: an alternating voltage source; a series resonant non-linear circuit including a saturable core inductor and a capacitance connected to said alternating voltage source; a control circuit connected across the capacitance of said series non-linear circuit, said control circuit including a second saturable core inductor connected in parallel with a second capacitance and in series with a third capacitance; a source of control signals; a control Winding for saturating the core of said second saturable core inductor in accordance with said control signals, said second saturable core inductor being in parallel resonance with said second capacitance to provide a high impedance when said control signal is low in potential, and being in series resonance with said third capacitance to provide a low impedance when said control signal is high in potential; and an output circuit connected across the capacitance of said series non-linear circuit.

l). A variable impedance loading circuit for connection across the output of an A. C. signal generator comprising: a saturable core inductor; a first capacitance connected in parallel with said inductor; a second capacitance connected in series with the parallel circuit formed by said inductor 'and said first capacitance; a control Winding for said saturable inductor; and a source of control signals applied to said control winding for controlling the saturation of said inductor; whereby said inductor is in parallel resonance with said rst capacitance to provide a high impedance across the output of said A. C. signal generator when said control signals are low in potential, and whereby said inductor is in series resonance with said second capacitance to provide a low impedance across the output of said A. C. signal generator when said control signals are high in potential.

No references cited. 

